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bubblesort1024ram
- 快速冒泡排序基于FPGA实现,有测试文件以及设计图,实现1024*32位数序的多数排序,突破传统是的REG类型少数排序,利用RAM,针对RAM中的无序数的地址调换,达到排序目的,仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
using_the_block_RAM_in_Spartan-3_FPGA
- Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
VHDL
- 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下: 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道(ch1、ch2、ch3、ch4),每个通道配备100 Bytes的RAM,当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出,输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道,DISPLAY
ShiftRegister
- Shift register verilog code
c51
- 51单片机,USB,触摸,TFT,的等综合应用,高级别。(usb+flash+touch+tft+ram综合测试)-51 single-chip, USB, Touch, TFT, integrated applications (usb+ flash+ touch+ tft+ ram General Test)
miffile
- 用matlab产生mif文件。(Altera的EDA软件,如maxplus,quartus等用到的初始化rom,ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
hh
- 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog descr iption of dual-port RAM of the verilog descr iption
HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
IDTContrl
- 该Verilog程序提供了一种控制IDT系列Ram的读写操作程序,每次读写750个16位的数。-The Verilog program control IDT provides a series of read and write operating procedures Ram, 750 each to read and write the number 16.
dds_easy
- 直接频率合成DDS模块的ise工程,可以直接下载,在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波,也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位,可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram,为节省储存空间仅需要储存1/4周期的数据。根据需要,可以重新修改数据,改变波形。-DDS direct frequency synthesizer module ,ise project, can be dir
bram_delay
- Verilog编写的代码,单口RAM用程序控制地址,而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
x3cs400_uart
- 基于X3cS400的串口通讯程序,开发环境ISE7.0,使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA, develop enviroment: ISE7.0,completed by verilog。 The result could be seen on the Uart debug assitant.
rom_prf_gen
- 用ram存储顺序,用此方法也可以实现其他的顺序数据,代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
verilog_RAM
- verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
shift_regeister
- 用blockram实现移位寄存器,开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
LIP2301CORE_Synthesisable-RAM
- Verilog Synthesisable RAM source code